IBM Debuts World's First Sub-1 Nanometer Chip Technology

IBM has unveiled what it calls a major semiconductor breakthrough with the introduction of the world's first sub-1 nanometer chip technology. Announced on June 25, 2026, from Yorktown Heights, New York, the technology features a revolutionary "nanostack" 3D chip architecture at the 0.7 nanometer, or 7 angstrom, node. This achievement marks a landmark moment for an industry facing the physical limits of traditional chip scaling, and it is expected to help propel the semiconductor industry forward for the next decade.^[1][2][3]

The new chip node—which refers to the manufacturing process and its design rules—can pack 100 billion transistors onto a chip the size of a fingernail. This is nearly twice the density of IBM's 2 nanometer node chip, which revolutionized the industry when it was first unveiled in 2021. Achieving a sub-nanometer scale has long been a key industry milestone on the path to producing smaller, more powerful, and more energy-efficient chips.^[1][3]

The names of transistor nodes now refer to generations of manufacturing technology rather than exact physical dimensions. In the case of this new technology, it involves atomic-level engineering. The transistors incorporate three sheets that are each 5 nanometers, or about 15 atoms, thick, to help push past traditional scaling limits.^[3]